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RM0008
Table 92.
Flexible static memory controller (FSMC)
NOR Flash/PSRAM supported memories and transactions (continued)
Device
PSRAM
(muxed I/Os
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
R/W
R
W
R
W
R
W
AHB
data
size
8
8
16
16
32
32
Memory
data size
16
16
16
16
16
16
Allowed/
not
allowed
Y
Y
Y
Y
Y
Y
Comments
Use of byte lanes NBL[1:0]
Split into 2 FSMC
accesses
Split into 2 FSMC
accesses
and nonmuxed
I/Os)
SRAM and
ROM
Asynchronous
page
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
R
R
R
R
W
W
R
W
-
8
16
32
8
16/32
8 / 16 /
32
8 / 16 /
32
16
16
16
16
16
16
8 / 16
8 / 16
N
N
Y
Y
Y
Y
Y
Y
Mode is not supported
Use of byte lanes NBL[1:0]
Use of byte lanes NBL[1:0]
Use of byte lanes NBL[1:0]
19.5.3
General timing rules
Signals synchronization
●
●
All controller output signals change on the rising edge of the internal clock (HCLK)
In synchronous write mode (PSRAM devices), the output data changes on the falling
edge of the memory clock (CLK)
19.5.4
NOR Flash/PSRAM controller timing diagrams
Asynchronous static memories (NOR Flash, SRAM)
●
●
●
Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
The FSMC always samples the data before de-asserting the chip select signal NE. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
When extended mode is set, it is possible to mix modes A, B, C and D in read and write
(it is for instance possible to read in mode A and write in mode B).
Doc ID 13902 Rev 9
417/995
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